Latch Based Interconnect Pipelining For High Speed Integrated Circuits

Aggressive optimization of global interconnect and various improvement skims, such as, repeater insertion, advancement of interconnect materials and use of low dielectrics constant materials are not sufficient to ensure the required performance of high-performance nanometer-scale integrated circuits, since interconnect delays will far exceed the device delays, and multiple clock cycles may be needed for cross-chip signal communication. Unconventional methodologies like insertion of sequential elements in interconnects lines -a concept that has become known as interconnect pipelining - are required to find acceptable solution beyond traditional buffer-insertion based interconnect systems. Here a survey of the issues and challenges in realizing interconnect pipelining technique are presented. Wire pipelining can be based on two approaches - edge triggered flip-flops based and transparent latch based pipelining. Here a set of analytical models is developed to study the implementation of latch based wire pipelining. The proposed analytical models can be used to predict the minimum number, position and feasible region of latches required for wire pipelining scheme