SRAM Circuit with Expanded Operating Margin and Reduced Stand-by Leakage Current Using Thin-BOX FD-SOI Transistors

We propose a low-power SRAM circuit using thin-BOX FD-SOI transistors. The SRAM circuit uses back-gate bias effectively, and acquires high operating margin and high speed operation under low supply voltage. The leakage current in standby state is reduced. This SRAM achieves 30% faster writing time under low-voltage operation, and 90% less stand-by power