IP Core Design of PLC Microprocessor with Boolean Module

This paper presents the IP core design of PLC (programmable logic controller) microprocessor that includes a special Boolean process unit after analysing PLC programming language, instruction execution characteristics and current PLC disadvantage. The novel microprocessor based on RISC architecture for PLC accords with PLCs international standard and its systematic design requirement. It is successfully synthesized and simulated with EDA tools and implemented in FPGA of Altera's EP20K200EFC484. As a microprocessor IP core for PLC, its particular design of memory bit access interface unit and Boolean processor unit can greatly improve the real time performance and stability for PLC, its design scheme and experimental result will contribute to further research and development of relevant products