A Digital Time Delay Measurement Technique and Phase-Locked Loop Requirements in a Standard CMOS Process

A digital architecture is proposed for measuring time delay increments much smaller than the clock period of a practical operating speed in a standard CMOS process. The technique employs correlated double sampling (CDS), a time-interleaved finite impulse response (FIR) averaging and infinite impulse response (IIR) noise filtering. A system with 200ns peak to peak delay deviation and 10-bit resolution requirement is presented in a 0.5mum CMOS process with an area estimate of 3.5 mm
²
and power estimate of 60 mW