Detection of Trap Generation in High-κ Gate Stacks due to Constant Voltage Stress

High-k gate stack reliability has become one of the critical factors impacting the introduction of advanced gate stacks in future technology nodes. A high density of as-grown electron traps in the transition metal oxides (Bersuker et al., 2004) and the presence of the SiO
₂
layer at the interface between the high-k dielectric and the substrate, complicate evaluation of stress-induced defect generation in high-k gate stacks (Lee et al., 2005), (Ribes et al., 2005). Effectiveness of stress-induced trap generation in high-k dielectrics remains a controversial issue, with the conclusions varying with the applied techniques and test conditions (Bersuker et al., 2004)-(Huo et al., 2004). Thus, there is a strong need to de-convolute the contributions to trap generation from the interfacial Si O
₂
layer (IL) and high-k film (Degraeve et al., 2003). In this study, by using a set of gate stacks with various combinations of the high-k film and ILs thicknesses, and a developed analysis methodology for charge pumping (CP) data, we identified the IL in the stack as the potential reliability "weak link"