65nm SOI CMOS Technology for High Performance Microprocessor Application

This paper presents a state-of-the-art 65nm SOI CMOS transistor technology target for high performance microprocessor application. N/PFET shows short channel control meeting manufacturing margin at 32/35nm respectively. By using dual contact etch stop layer (CESL) process, PFET ion is 875muA/mum at I
_off
=100nA/mum (V
_DD
=1.2V), which is 65% increase over 90nm node. The 65nm technology also offers SRAM cell sizes ranging from 0.499mum
²
to 0.64mum
²
for various speed and density requirement