A 1.9-GHz Single-Chip CMOS PHS Cellphone

A single-chip CMOS PHS cellphone, integrated in a 0.18-<formula formulatype="inline"> <tex>$\mu{\hbox {m}}$</tex></formula> CMOS technology, implements all handset functions including radio, voice, audio, MODEM, TDMA controller, CPU, and digital interfaces. Both the receiver and transmitter are based on a direct conversion architecture. The RF transceiver achieves <formula formulatype="inline"> <tex>$-$</tex></formula>106 dBm receive sensitivity and <formula formulatype="inline"> <tex>$+$</tex></formula>4 dBm EVM-compliant transmit power. The local oscillator, based on a sigma-delta fractional-<emphasis>N</emphasis> synthesizer, has a phase noise of <formula formulatype="inline"><tex>$-$</tex></formula>118 dBc/Hz at 600 kHz offset and settling time of 15 <formula formulatype="inline"><tex>$\mu{\hbox {s}}$</tex></formula>. The current consumption for the receiver, transmitter and synthesizer are 32 mA, 29 mA, and 25 mA , respectively, from a 3.0 V supply.