Total dose radiation hardening and testing issues of GaAs static memories

A test chip in GaAs (E/D) technology has been designed and implemented in 1.2 /spl mu/m MOSIS GaAs design rules. The unpackaged devices have been subjected to 1.5 keV Al-K/sub /spl alpha// X-rays and degradations in zero bias threshold voltage and device transconductance of n-channel E and D-MESFETs have been studied. A modified GaAs SRAM cell design, incorporating a circuits design to minimize degradations in noise margin due to degradations in device parameters at large radiation doses has been proposed.<
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