High quality SiO/sub 2//Si interfaces of poly-crystalline silicon thin film transistors by annealing in wet atmosphere

A new post-metallization annealing technique was developed to improve the quality of metal-oxide-semiconductor (MOS) devices using SiO/sub 2/ films formed by a parallel-plate remote plasma chemical vapor deposition as gate insulators. The quality of the interface between SiO/sub 2/ and crystalline Si was investigated by capacitance-voltage (C-V) measurements. An H/sub 2/O vapor annealing at 270/spl deg/C for 30 min efficiently decreased the interface trap density to 2.0/spl times/10/sup 10/ cm/sup -2/ eV/sup -1/, and the effective oxide charge density from 1/spl times/10/sup 12/ to 5/spl times/10/sup 9/ cm/sup -2/. This annealing process was also applied to the fabrication of Al-gate polycrystalline silicon thin film transistors (poly-Si TFT's) at 270/spl deg/C. In p-channel poly-Si TFT's, the carrier mobility increased from 60-400 cm/sup 2/ V/sup -1/ s/sup -1/ and the threshold voltage decreased from -5.5 to -1.7 V.<
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