The modified structure of the lateral IGBT on the SOI wafer for improving the dynamic latch-up characteristics

The modified structure of the lateral IGBT(LIGBT) on an SOI wafer for improving the dynamic latch-up characteristics is presented together with its numerical simulations and experimental results. The modified LIGBT structure has a p/sup +/-emitter layer between the collector and gate regions. The current at which the latch-up occurs during the turn-off transient under an inductive load is estimated in comparison with that of the conventional LIGBT. The dynamic latch-up current at room temperature and 125/spl deg/C for the modified LIGBT were 350 A/cm/sup 2/ and 290 A/cm/sup 2/, respectively. These results indicate the improvement of about 3.5 times at room temperature and about 5.5 times at 125/spl deg/C compared with those for the conventional LIGBT. This remarkable improvement in the dynamic latch-up performance is accomplished at the expense of an increase of 0.8 V in the forward voltage drop.<
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