Testability strategy for registers and memories in a multi-processor architecture

A testability strategy is presented for registers and memories embedded in multiprocessor chips designed with the Cathedral-II silicon compilation environment. The implementation requires the design of a scan register that is able to maintain a value at its output while scanning a vector into the scan chain. A test algorithm for the register file, based on the concept of C-testability, is derived. The fault model covers both stuck-at and most of the transistor stuck-open and stuck-close cases. In addition, large embedded memories are important in processor systems. A test strategy with very high fault coverage is implemented with a self-test approach.<
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