Mixed level test generation for MOS circuits

The authors present a test-generation system for combinational circuits described at mixed gate and switch levels. The circuit under test is hierarchically partitioned into blocks characterized by their I/O function. Only the faulty block is eventually expanded to perform fault injection. The algorithm also exploits dynamic partitioning and adaptive backtrace to speed up the test search. Robust tests for stuck-open faults are derived with the help of a ternary simulation technique. Preliminary results show that on large circuits a saving of an order of magnitude can be expected in CPU time when compared with performance on a flat gate-level implementation.<
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