A boron-retarding and high interface quality thin gate dielectric for deep-submicron devices

We report the fabrication and device characteristics of a 50 /spl Aring/ thick dual-layer gate dielectric with high interface quality (D/sub it/ and Q/sub f/ /spl sim/10/sup 10/ cm/sup 2/) and capable of retarding boron penetration. This dual-layer dielectric is formed by low temperature CVD deposition of a /spl sim/40 /spl Aring/ thick oxynitride layer, through which slow O/sub 2/ diffusion is used to grow a /spl sim/10 /spl Aring/ thick SiO/sub 2/ at the interface. The small thickness of the SiO/sub 2/ layer reduces the oxidation time at high temperature, thus reducing the required thermal budget. The top oxynitride retards boron penetration and the thin SiO/sub 2/ layer provides a high quality interface. The channel mobility of NMOS devices with this dual dielectric is equal to the mobility of devices with a RTO dielectric grown at 950/spl deg/C.<
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