Bus arbitration in an embedded processor-shared multiprocessor system

Bus arbitration scheme for a partially processor shared-memory system embedded in a general reconfigurable R(n,m) system is presented where n is the number of global processors, and m is the number of global memory modules. The effective cost for the arbitration and crosspoint switch control is absorbed within the hardware implementation of a SIMD array processor which can be used as a crosspoint switch controller. This embedded system shows an improvement of bandwidth over conventional group based bus systems.<
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