A quadruple well, quadruple polysilicon BiCMOS process for fast 16 Mb SRAM's

An advanced, high-performance, quadruple well, quadruple polysilicon BiCMOS technology has been developed for fast 16 Mb SRAM's. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61 /spl mu/m/sup 2/ with conventional I-line lithography and 7.32 /spl mu/m/sup 2/ with I-line plus phase-shift or with deep UV lithography. The process features PELOX isolation to provide a 1.0 /spl mu/m active pitch, MOSFET transistors designed for a 0.80 /spl mu/m gate poly pitch, a double polysilicon bipolar transistor with aggressively scaled parasitics, and a thin-film polysilicon transistor to enhance bitcell stability. A quadruple-well structure improves soft error rate (SER) and allows simultaneous optimization of MOSFET and bipolar performance.<
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