Improving CMOS speed at low supply voltages

A common approach to reduce CMOS power consumption is to reduce the supply voltage. However, circuit speeds degrade rapidly as the supply voltage drops. This paper uses theoretical analyses and experiments to explore the effectiveness of circuit and process modifications for improving speed at low V/sub DD/. In particular, we find that circuits operating in ohmic mode have less speed-V/sub DD/ sensitivity and thus run faster at low supply voltages.<
>