A 30-ns cycle time 4-Mb mask ROM

A 4-Mb mask ROM in a 256-Kb/spl times/16 organization is described. It is fabricated with a 1.0-/spl mu/m CMOS process, using single polysilicon, two levels of metal, and 3.0/spl times/4.4 /spl mu/m/sup 2/ X-cells. Unlike conventional ROM's, it implements a DRAM type RAS/CAS control scheme. A RAS access time of 60 ns is measured. For a fast data access, the chip has a consecutive address read mode in which the system needs to supply only a first address and subsequent addresses are generated in the ROM chip at every CAS clock. A 30-ns cycle time is demonstrated in this mode. 16-b data pins are also used for RAS/CAS multiplexed address inputs. Because of this three way pin multiplexing, the 7.5/spl times/10.5 mm/sup 2/ chip needs only 28 pins for its 400-mil SOJ package.<
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