A 1- mu m polysilicon self-aligning bipolar process for low-power high-speed integrated circuits

A double-poly-Si self-aligning bipolar process employing 1- mu m lithography is developed for very-high-speed circuit applications. Epilayer doping and thickness are optimized for breakdown voltages and good speed-power performance. Shallow base-emitter profiles are obtained by combining low-energy boron implantation and rapid thermal annealing (RTA) for the emitter drive-in. A transit frequency f/sub T/=14 GHz at V/sub BC/=-1 V and a current-mode-logic (CML) gate delay of 43 ps at 30 fJ are achieved. For an emitter size of 1.0*2.0 mu m/sup 2/ a minimum power-delay product of 15 fJ is calculated. Circuit performance capability is demonstrated by a static frequency divider operating up to 15 GHz.<
>