A high-performance quadruple well, quadruple poly BiCMOS process for fast 16 Mb SRAMs

An advanced, high-performance BiCMOS technology has been developed for fast 16Mb SRAMs. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61 mu m/sup 2/ with conventional i-line lithography and 7.32 mu m/sup 2/ with i-line phase-shift lithography. The process features PELOX isolation to provide a 1.0 mu m active pitch, MOSFET transistors designed for a 0.80 mu m gate poly pitch, a double polysilicon bipolar transistor with aggressively scaled parasitics, and a thin-film polysilicon transistor to enhance bitcell stability. A quadruple-well structure improves soft error rate (SER) and allows simultaneous optimization of MOSFET and bipolar performance,.<
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