A half-micron super self-aligned BiCMOS technology for high speed applications

We report the process design, device characteristics and circuit performance of a new ultra high speed, high density, half-micron super self-aligned BiCMOS technology. The minimum CMOS gate delay was measured to be 38 psec on 0.5 mu m gate and 50 psec on 0.6 mu M gate ring oscillators at 5 volt. Bipolar gate delay was measured to be 31 psec on a 0.6 mu m emitter ECL ring oscillator. A single phase decision circuit operating error free at 8 Gb/sec and a static frequency divider operating above 10 Gb/sec were demonstrated in our BiCMOS technology.<
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