Design for concurrent error detection and testability in storage/logic arrays

Storage/Logic Arrays (SLA's) represent a structured logic array approach to the design of VLSI sequential logic. Design for concurrent error detection and testability is complicated in these arrays by the presence of embedded memory elements and multiple levels of logic. A means of designing SLA's for ease of testability and concurrent error detection (CED) is provided in this paper. Test sets for static and dynamic CMOS circuits are described. Fault and error coverage is presented and performance and area costs are analyzed for example circuits. In addition, a means of implementing dynamic CMOS SLA's is presented and shown superior to previous NMOS, static CMOS, and dynamic CMOS approaches based upon power consumption and simplicity of design.<
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