CMOS implementation and fabrication of the pseudo analog neuron

The pseudo-analog neuron (PAN) uses a transresistance amplifier and multivalued logic design techniques to implement the basic building blocks of artificial neural networks. The performance characteristics of PAN building blocks that were implemented in a standard 2- mu m CMOS process are described. A two-layer network of PANs is used to implement various Boolean functions. The two-layer circuit computes ten weighted sum of inputs plus four thresholds in the first layer, and a four weighted sum plus one threshold in the second layer. All thresholding and weighted sums are propagated in 10 ns through both layers. This circuit dissipates 250 mu W of average power, and occupies 288 mu m*136 mu m of silicon area.<
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