Improved prediction of interface-trap generation in NMOST's

Hot-carrier-induced interface-trap generation in NMOSFET's is a serious reliability hazard for CMOS circuits. Its prediction has been either inaccurate or it needed many process dependent fitting parameters. We introduce a new method that improves lifetime prediction by orders of magnitude. Our method requires no additional fitting parameter and is applicable in existing circuit simulators. From the (time dependent) voltages and currents, available in a circuit simulator, we predict the number of generated interface traps. Our prediction method has been checked in more than a hundred experiments on NMOSFET's with 0.2-2.0-μm length, 0.8-10-μm width, and 5.5-25-nm oxide thickness.