A 1.5-ns cycle-time 18-kb pseudo-dual-port RAM with 9K logic gates

An 18-kb RAM with 9-kgate control logic gates operating during a cycle-time of 1.5 ns has been developed. A pseudo-dual-port RAM function is achieved by a two-bank structure and on-chip control logic. Each bank can operate individually with different address synchronizing the single clock. A sense-amplifier with a selector function reduces the reading propagation time. Bonded SOI wafers reduce the memory-cell capacitance, and this results in a fast write cycle without sacrificing /spl alpha/-particle immunity. The chip is fabricated in a double polysilicon self-aligned bipolar process using trench isolation. The minimum emitter size is 0.5/spl times/2 /spl mu/m/sup 2/ and the chip size is 11/spl times/11 mm/sup 2/.<
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