A CAD procedure for optimizing bipolar devices relative to BiCMOS circuit delays

Proposes an optimization procedure for the bipolar base doping profile for a high-speed BiCMOS circuit. This procedure aims to achieve the minimum propagation delay time, taking the power supply, the load capacitance, and the bipolar device layout into consideration. For a small load capacitance, the peak base doping concentration and the base width should be as small as possible. However, for a high load capacitance, the optimized base doping profile can vary under the emitter area constraint. Utilizing this optimization procedure, it will be shown that the propagation delay time can be reduced by more than 30% at the same MOS current (I/sub MOS/=1 mA) through the coordinated reduction of both the vertical doping profile and the horizontal dimensions of the bipolar transistor, with the power supply voltage scaled from 5 to 3.3 V.<
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