4B5B decoder for FDDI

A 2- mu m CMOS FDDI (fiber distributed data interface) 4B5B decoder with an elastic self-timed buffer is presented. The design operates at 125 MHz and meets the requirements specified by the ANSI X3.139-1987 standard. The characteristic features of this design are logical simplicity, compact silicon area, operational speed well above that specified for FDDI, and metastable operation resistivity. These features have been obtained by self-timed implementation of the elastic buffer.<
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