Development and simulation of a 4080-point Winograd fast Fourier transform processor

By using the Good-Thomas prime factor algorithm, 15-, 16-, and 17-point Winograd algorithm fast Fourier transform (FFT) processors are combined to perform 4080-point FFTs. The circuits are analyzed in VHSIC hardware description language (VHDL), simulated, and laid out in MAGIC for fabrication through MOSIS. The VHDL simulation includes behavioral modeling and the simulation of 15-, 16-, 17-, and 4080-point FFT problems. Two of the three FFT processors are submitted for fabrication using a 1.2- mu m CMOS process.<
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