The COREWARE methodology: building a 200 MFLOP processor in 9 man months

Utilizing the COREWARE methodology, a 163-MFLOP graphics transformation processor is realized in a 0.7- mu m two-layer metal CMOS process operating at 40 MHz. The COREWARE methodology allows the processor to be specified, designed, and implemented in nine man months. The graphics processor provides 3.3 million transformed, perspective divided, clip tested 3D vertices per second. The matrix multiplication is based on the interleaved multiplier accumulator algorithm, which transposes the order of the arithmetic operations to accomplish maximum throughput.<
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