A VLSI-chip for a hardware-accelerator for the simplex-method

A hardware realization of the simplex method, the central method of linear programming, a presented. the algorithm is customized for numerical stability (arithmetics) as well as hardware proximity. The resulting hardware is based on a parallel architecture with up to eight processing units, employing standard floating point units (FPUs), RAMs, and custom VLSI chips. It has been designed for use in an IBM PC/AT environment.<
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