Fast address generation for the computation of prime factor algorithms

The authors propose an address generation scheme for in-place in-order prime factor algorithms. This scheme achieves high efficiency by using simple indirect addressing techniques to replace complicated modulo operations of previous methods. It is shown that the scheme is most suitable for software realizations using assembly languages. A hardware address generator based on this mapping scheme is also suggested. Its architectural simplicity makes it suitable for fabrication as a single-chip peripheral to add onto current digital signal processors or to be integrated into future DSP (digital signal processor) architectures. In both cases, a 30% to 50% reduction in computation time is achievable in the realization of prime factor algorithms using digital signal processors.<
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