Novel circuits for radiation hardened memories

Novel circuits, including orthogonal-shuffle-type write-read arrays, error correction by weighted bidirectional codes, and associative iterative repair circuits, are proposed for significant improvements of static random-access memory (SRAM) immunity against the effects of total dose and cosmic particle impacts. The implementation of the proposed circuit resulted in fault-tolerant 40-Mb and 10-Mb monolithic memories featuring a data rate of 120 MHz and power dissipation of 880 mW. These experimental serial-parallel memories were fabricated with a nonhardened standard CMOS processing technology, yet provided a total dose hardness of 1 Mrd and a projected SEU rate of 1*10/sup 12/ error/b/day. Using radiation-hardened processing, improvements by factors of 10 to 100 are predicted in both total dose hardness and SEU rate.<
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