An experimental comparison of different approaches to ROM BIST

The issue of ROM testing in VLSI circuits is examined. The BIST (built-in-self-test) solution overcomes controllability and observability difficulties which represent the limits of conventional ATPGs (automatic test pattern generators) and becomes particularly suitable for deeply embedded ROMs. The classical approach is studied, and a novel solution which tries to minimize the masking effect of faults in the additional external logic is proposed. Preliminary results are also reported, related to some BIST implementations of ROMs with different dimensions, and the area overhead due to the BIST logic is carefully evaluated. A macro generator which produces the BIST block without any intervention of the IC designer, starting from ROM characteristics, is presented.<
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