Gate usage strategies applied to BiCMOS sea-of-gates arrays

A methodology for comparing CMOS and BiCMOS gate usage strategies is applied to gate delay optimization. Advanced strategies mixing simple and buffered CMOS and BiCMOS gate configurations are shown to be significantly superior, in terms of speed and density, to full-CMOS or full-BiCMOS strategies. For typical capacitance distributions, the speed advantage can be as high as 70% compared to a pure BiCMOS solution. A similar method can be used to minimize area or power dissipation. A BiCMOS sea-of-gates master, designed by using this method, is presented.<
>