Concurrent error detection of CMOS digital and analog faults

The authors present a novel approach to designing TSC (totally self-checking) CMOS circuits, considering transistor stuck-on faults. Their approach is delineated by a design-for-testability (DFT) technique, which requires a very small constant number of extra transistors, coupled with a simple clocking scheme, to detect the stuck-on faults concurrently. The DFT circuitry can defect the faults in the functional circuit and it can detect or tolerate the faults in itself.<
>