Functional memory array testing using associative search algorithms

To accelerate functional memory array testing in advanced workstations, a conventional memory array is proposed to be modified using circuit structures known from flag-oriented associative memories. Thus memory array lines can be tested in parallel using associative search operations. All memory chips are tested in parallel using conventional tests. The drastic test speed up due to the new approach is discussed and the structure of an AT-bus memory board implementation is presented.<
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