Fast partitioning method for PLA-based architectures

Describes a method for automatic partitioning of a given multioutput function into the smallest number of subfunctions such that each subfunction can fit into a fixed size PLA or functional block of a given field programmable gate array (FPGA) chip. The proposed method is fast, efficient and produces almost optimum partitions for the examples which have been tried. The partitioning procedure is in production use as part of an automated design system at Plus Logic.<
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