1-micron ASIC technology achieves greater than 4000 volts electrostatic discharge protection

Sources of electrostatic discharge (ESD) are many. They include differences in triboelectric charge from dissimilar materials, atmospheric charges resulting from temperature gradients or electric/magnetic fields. ESD levels of thousands of volts can result and cause catastrophic device damage either during device manufacturing or at system- or board-level handling and testing. Circuit design considerations for CMOS I/O structures as well as good ESD handling procedures are required to control ESD damage and provide ESD immunity to greater than 4000 volts.<
>