A sub-micron ECL gate array family

A new ECL gate array family was developed with 50ps typical gate delay under 1 mA switching current. It pushes the gate count to over 100K gates with 320 I/O signal pads. The process used is National Semiconductor's fourth generation, 0.8 mu m ASPECT III process. A frequency divider test with 0.6mA switching current was used to prove the input frequency exceeds 2.5 GHz for the first time utilizing silicon technology. With interconnect delay at 1 ps/mil, this ECL gate array family is optimized for VLSI designs.<
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