Bit-serial multiplier based on Josephson latching logic

The authors have designed, fabricated, and tested a Josephson bit serial multiplier based on voltage latching logic. The bit serial implementation takes advantage of high-speed characteristics of Josephson circuits to achieve higher circuit functionality per gate by reducing gate complexity. To facilitate the multiplier design, logic simulation was performed using transistor-transistor-logic (TTL) equivalent gate models of voltage latching modified-variable-threshold-logic (MVTL) gates. A 4-b serial-parallel multiplier based on MVTL gates has been designed and fabricated in niobium. The basic timed-XOR and full adder circuits used in the multiplier were successfully tested. Preliminary testing of the multiplier indicated inadequate operating margin for a full functional test.<
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