ASIC design of a high performance RISC

Describes the VLSI implementation of a 32-bit central processing unit (CPU) chip based on reduced instruction set computer (RISC) principles and its testing methodology based on functional fault model. The processor which adopts 4-stage instruction execution pipeline has achieved the goal of single cycle execution using a 2-phase 16.7 MHz clock. The cell-based approach was chosen as VLSI implementation scheme of SPARK RISC CPU. Performance simulation shows that this architecture achieves a scalar performance of 16.7 MIPS (million instructions per second) peak. This chip is implemented with 1.0 mu m double layer metal CMOS technology and consists of about 150 K transistors.<
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