A fast pipelined complex multiplier: the fault tolerance issues

A comprehensive discussion of a dedicated device for serial complex multiplication is presented, covering architectural, reliability and fault tolerance properties. The pipelined architecture is briefly described. It is optimized w.r.t. several figure of merits: clock rate, external pipelining and pipeline filling degree. Testability features are analyzed under functional fault models by means of graph-theoretic methods, showing full testability of the device. Error detection is introduced by means of arithmetic codes and the tradeoff between error detection and cost is evaluated. Eventually on-line reconfiguration is introduced through the Diogenes approach and the tradeoff between fault tolerance and cost is also discussed. Discussion are based on analytic interpolation software simulation and the evaluation of prototypal layouts in CMOS technology.<
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