CMOS implementation of an analogically programmable cellular neural network

The criteria for designing the basic building blocks of an analogically programmable cellular neural network (CNN) in a 1.5- mu m CMOS technology are reported. The simulated electrical performances of a 10*10 CMOS CNN, consisting of about 8000 MOS transistors, are presented and discussed. It is shown that the designed CNN can be successfully used to perform such useful functions as noise removal, edge detection, hole filling, shadow detection, and connected component recognition.<
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