An associative memory approach to parallel logic event-driven simulation

Presents a parallel processing approach to logic simulation, called APPLES, in which gate evaluations and signal updating are executed in parallel in associative memory, rather than in the processor. This approach does not require any event scheduling mechanism and can model various logic gate types and delay models. Two concepts are coupled together to form a parallel acceleration technique in the simulator. The first concept deals with representing signals on a line over a period of time as a bit-sequence. This sequence representation can be incorporated into evaluating the output of any logic gate, by comparing the bit-sequences of its inputs with a predetermined series of bit patterns. Numerous bit operations, such as shifting and comparing, must be performed in parallel on the input bit-sequences of various logic components. The second concept, that of an associative memory with word shift capabilities, is really a hardware implementation of these bit operations. Therefore, these concepts are presented as an abstract model followed by its physical realization. APPLES has been simulated at a behavioral and gate level description in System-Hilo.<
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