On the construction of very large integer multipliers

In this paper the authors present a fast shared multiplier for very large numbers. Realizing this concept for any input length (e.g. 512, 1024 or 2048 bits) only needs three types of chips. One of them is a 32-bit multiplier which does not require any more development. They expect a speed up of factor 100-1000 (dependent on the input length) in comparison to a simulation by software. A further speed up of applications using many independent multiplications can be attained by pipelining the multiplier. The 1024-bit multiplier can be realized using only four platines at a rough estimate. The multiplier itself has yet to be realized.<
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