A test vehicle for monitoring and improvement of CMOS reliability performance

Monitoring reliability performance through accelerated testing on products is at least incomplete and failure analysis is difficult. Device level reliability stress tests are an attractive complement, and offer a wider range of overstresses, a clearer relationship between stress and failure, and reduced stress times. A 2.0 micron CMOS testchip has been built, containing stress patterns for interconnect, dielectrics, diffusions and transistors. A set of stress conditions has been designed, and data handling software has been developed to analyse parameter shifts due to ageing and assembly. The system is used for monitoring and for evaluation of process changes.<
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