A 140 Mb/s 32-state radix-4 Viterbi decoder

Applications in trellis code demodulation for communication channels and digital sequence detection for magnetic storage devices generate interest in implementation of the Viterbi algorithm at around 100 MHz. An important decoding problem found in both applications is the binary shift register trellis. The classical high-throughput implementation for such decoders is the radix-2 state-parallel approach, where add-compare-select (ACS) units are assigned to each state and organized in pairs to iterate one stage of a 2-state trellis. The decode rate is fundamentally limited by either the recursive ACS iteration or the recursive traceback iteration. To date, such single-chip implementations have been limited to a decode rate of 25 Mb/s. In the present work, the throughput has been extended in an area-efficient manner by applying one stage of lookahead to both the ACS and traceback recursions. This architecture is demonstrated in a 32-state, radix-4 Viterbi decoder achieving 140 Mb/s decode rate.<
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