A system-integrate ULSI chip containing eleven 4 Mb RAMs, six 64 kb SRAMs and an 18 k gate array

The authors describe the realization of a ULSI chip that makes system integration possible on a silicon die, not in wafer-scale integration. They consider chip configuration, packaging, defect relief, fabrication, and evaluation results. This system-integrated ULSI chip (SYSI-ULSI) contains eleven standard 4-Mb DRAMs, six standard 64-kb SRAMs, 200 I/O pins, and an 18-k gate array. The DRAMs are laid out on both sides of the chip. The 200 I/O pins are located on the upper and lower sides of the chip, and the gate array is laid out at the center to reduce the length of the channel between it and each part and eliminate skew between channels by equalizing their lengths. The 38.16*50.4 mm/sup 2/ SYSI-ULSI chip is packaged in a 324-pin 54*86 mm/sup 2/ plastic grid array package. A Cu/W thermal spreader is used for die-bonding. A cavity-down package is used for low thermal resistance with a heat sink. Power dissipation is 3.9 W.<
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