0.5 mu m BiCMOS standard-cell macros including 0.5 W 3 ns register file and 0.6 W 5 ns 32 kB cache

BiCMOs standard-cell macros, including a 0.5-W, 3.0-ns register file, a 0.6-W, 5.0-ns 32-kB cache, a 0.2-W, 2.5-ns table look-aside buffer (TLB), and a 0.1-W, 3.0-ns adder, are presented based on a 0.5- mu m BiCMOs technology. These power consumption values are at 100 MHz operation. Low power and high speed are crucial for high-performance systems requiring a high level of integration. Several BiCMOS/CMOS circuits achieve high-speed operation with a 3.3-V supply. A direct-coupled ECL (emitter-coupled logic)+CMOS circuit is investigated for use as a BiCMOS standard cell.<
>