A novel test structure for monitoring technological mismatches in DRAM processes

Based on a typical 1 6-Mb dynamic-RAM (DRAM) sense amplifier using 0.6- mu m design rules, a test structure was designed and the minimum signal voltage for reliable operation of the sense amplifier was determined. The analysis of the measured data provides a monitor for DRAM process control. Variations in gate lengths and capacitances and the influence of the decoupling transistors located between bitlines and sense amplifier were investigated. The local variation in threshold voltage was investigated on a separate test structure on the same wafer. In this way the contribution to the minimum sense signal attributed to mismatches in current gain and parasitic transistor capacitances can be separated. The minimum storage cell capacitance for which correct sensing was possible was determined.<
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