Transistor-level CMOS gate models for timing analysis and simulation

The authors developed a transistor-level CMOS gate model which predicts output transition and delay times with an accuracy which is usually within 10% of SPICE. The model uses constant grounded capacitors to account for storage effects, which makes it applicable in timing analysis and simulation programs which use point-relaxation solution techniques. The authors present the model for a CMOS inverter, which then serves as the basis for modeling CMOS NAND and NOR gates, where the intermediate node capacitances have to be considered.<
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